Digital Acoustics ESBx-110 Especificaciones Pagina 208
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Control Block Description
ADDvantage-32 PLUS
4-78
4.54 PROPORTIONAL AND INTEGRAL CONTROL WITH
CASCADED HOLD BITS (PI2)
The PI2 block performs a proportional and integral gain function on an error signal. It
has inputs for maximum and minimum limits which prevent the loop from
overcompensating as well as separate bits to hold the integrator in either the positive or
negative direction only.
FIGURE 4-54. PI2 BLOCK
1. Inputs Data Type Description
ERR: Analog Input Signal
P: Analog Proportional Gain Value
I: Analog Integral Gain Value
MAXL: Analog Output High Limit Value
MINL: Analog Output Low Limit Value
PREL: Analog Integrator Preload Value
H-UP: Bit Integrator Positive Hold Enable
H-DN: Bit Integrator Negative Hold Enable
PRE: Bit Integrator Preload Enable
+
+
+
+
ERR ERR>0 MAX
ERR<0 MIN
P
I
PRE
PREL
IERR
MINL
MIN
OUT
MAXL
MAX
PIBLOCK
- ADDvantage-32 PLUS 1
- AC TO DC POWER CONVERTER 1
- PROPRIETARY NOTE 2
- WARRANTY 2
- SAFETY SUMMARY 4
- Safety Summary 5
- SECTION I 8
- INTRODUCTION AND 8
- GENERAL INFORMATION 8
- D C 0 0 3 0 - 4 Z 0 0 - B 33
- 6 9 6 0 0 2 . V 1 0 33
- 1.5 SPECIFICATIONS 37
- DESCRIPTION SPECIFICATION* 37
- DRIVE PART NUMBER 43
- SECTION II 47
- KEYBOARD AND 47
- PARAMETER FUNCTIONS 47
- PARAMLAYD105 54
- SECTION III 81
- CORE SOFTWARE OPERATION 81
- Core Software Operation 100
- number must be entered 112
- TurnsSecondaryCT 117
- OUTCTARM:***X = 117
- Ohms5*Turn1 117
- Turns4000 117
- Burden Resistor Waveform 121
- (Discontinuous Current) 121
- DCAFMC5LAN 121
- SECTION IV 129
- CONTROL BLOCK DESCRIPTION 129
- Table of Contents 129
- Table of Contents (Cont.) 130
- Control Block Description 132
- 8BITINVD101 139
- ANALOG SELECT 142
- ANLOGSELLAN 142
- BIT INVERT 150
- BITINVRT 150
- 3. Implementation 155
- 4.18 CLAMPING 156
- 4.19 COM LOSS 158
- 4.21 COMPARATOR 160
- 4.22 COPY 161
- 4.23 CURRENT LIMIT 162
- 165
- 4.24 DEADBAND 166
- 4.25 DEMUX 167
- 4.26 DENSITY 168
- 4.27 DERIVATIVE GAIN (D/DT) 170
- 4.28 DIFF TRIP 171
- 4.29 DIGITAL IN 173
- 4.30 DIGITAL OR 175
- 4.31 DIVIDE 176
- 4.32 DROOP 177
- Implicit 179
- 4.34 ERROR 180
- 4.35 FREQUENCY OUT 181
- 4.36 GAIN 182
- 4.37 HI/LOW COMPARATOR 183
- 4.38 IIT 185
- FIGURE 4-38. IIT BLOCK 186
- 4.39 LATCH 187
- 4.40 LEAD/LAG 189
- 4.41 LEAST WIN 191
- 4.42 LOWPASS FILTER 192
- 4.43 MOST WIN 193
- 4.44 MOV8 194
- 4.45 MULTIPLY 196
- 4.46 NOTCH FILTER 197
- 4.47 OFF TIMER 199
- 4.48 ON TIMER 200
- 4.49 ONE SHOT 201
- 4.50 PEAK DETECT 202
- 4.51 PERCENT DIFFERENCE 203
- )( INPPER 204
- CASCADED HOLD BITS (PI2) 208
- 4.55 QUAD LTCH 211
- 4.56 RAMP 212
- 4.57 RATE CHANGE 214
- 4.58 RATIO 215
- 4.59 RECIPE 217
- 4.60 RESOLVER 1 219
- 4.61 RMP2 222
- 4.62 RRAMP3 230
- 4.63 SDS SHEETS DURING STOP 233
- 4.64 SETPOINT 235
- 4.65 SNAPAVG 238
- FIGURE 4-65. SNAPAVG BLOCK 239
- 4.66 SPLICER 240
- 4.68 TABLE 243
- W A R N I N G 248
- 4.70 TIMER 249
- 4.71 TYPE 2 DIA 251
- 4.72 TYPE 3 DIA 253
- UNITYSCL 255
- 4.74 UV PROTECT 256
- 4.75 WINDER WK/D 258
- 4.76 WINDOW COMPARE 260
- SECTION V 263
- SIGNAL ANALYZER 263
- Signal Analyzer 264
- SECTION VI 273
- PREPARATION FOR USE 273
- Preparation for Use 274
- H2 H3 H1 283
- SMARTach Alarm 296
- ADD-32 PLUS Drive 296
- SECTION VII 299
- MAINTENANCE AND 299
- TROUBLESHOOTING 299
- TABLE 7-2. POWERUP MESSAGES 304
- SCRTEST1LAN 328
- (510 ADC and Below) 333
- INCORRECT 342
- "A1" 348
- TABLE 7-9. VENDOR GUIDE 352
- SECTION VIII 357
- IEEE 802.3 ETHERNET 357
- COMMUNICATION 357
- SECTION IX 391
- SYSTEM DATA STRUCTURES 391
- System Data Structures 392
- TABLE 9-1. DATA FILES 393
- SECTION X 411
- SERIAL LINK INSTALLATION 411
- AND TROUBLESHOOTING 411
- SECTION XI 419
- USB USAGE 419
- USB Usage 420
- USB FLASH LOAD 426
- ------> 426
- USB FLASH LOAD 428
- UP KEY TO CONFIRM 428
- USB DGNOST STORE 431
- USB D 433
- INFO SAVE 433
- USB CAL LOAD 436
- UP Key to Confrm 436
- USB CAL STORE 437
- FILE:CAL_SAVE_01 438
- SECTION XII 441
- UPGRADE TO NEW CONTROL 441
- Upgrade to New Control Board 442
- LED indicators 443
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